Memory hierarchy & Cache · Mind & Machine

MEMORY HIERARCHY SIMULATION

▸ Building the pyramid: registers · L1 · L2 · L3 · RAM · disk…

▸ Loading real latencies (≈1 → millions of cycles)

▸ Initializing the cache & LRU eviction policy

▸ Generating access patterns (sequential · scattered · hot loop)

▸ Calibrating hit / miss counters & average latency…

▸ Ready — Online. ✅

Hit rate & latency

🎲 Mixed access

Accesses—

Hits L1·L2·L3—

Misses (→RAM)—

Hit rate—

Avg latency—

Served from—

Notes

A computer arranges memory into many tiers: the closer to the CPU, the faster but smaller & pricier. The cache keeps copies of hot data so most accesses hit a fast tier; only a small fraction must go to RAM/disk. Whether a program is fast or slow depends on the locality of its accesses.

—

Pick a "Scenario" to change the access PATTERN (sequential · scattered · hot loop · too large · cold) · watch the packet descend to find data (hit=green, miss=red) · click a tier/concept for details

Your browser has canvas disabled.

Hit rate & average latency over time hit rateavg latency